(1) Field of the Invention
It is the object of the present invention to provide processes wherein special Alxe2x80x94Cu bond layers or regions are placed on top of the underlying copper pad metal. These Alxe2x80x94Cu bond pads on pure copper (with barrier layer in-between) provide for improved wire bond adhesion to the bond pads and prevent peeling during wire bond adhesion tests.
(2) Description of Related Art
An important challenge in the fabrication of wire bond pads is to have good adhesion and compatibility of the various metal layers in dual damascene processing. The damascene processing is a xe2x80x9cstandardxe2x80x9d method for fabricating planar copper interconnects. Damascene wiring interconnects (and/or studs) are formed by depositing a dielectric layer on a planar surface, patterning it using photolithography and oxide reactive ion etch (RIE), then filling the recesses with conductive metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with metal. For example, damascene wiring lines can be used to form bit lines in DRAM devices, with processing similar to the formation of W studs in the logic and DRAM devices. In both examples, sputtered Ti/TiN liners, underlying diffusion barriers, have been coated with chemical vapor deposited (CVD) W metal, then polished back to oxide.
In the dual-damascene process, a monolithic stud/wire structure is formed from the repeated patterning of a single thick oxide film followed by metal filling and CMP. First, a relatively thick oxide layer is deposited on a planar surface. The oxide thickness is slightly larger than the desired final thickness of the stud and wire, since a small amount of oxide is removed during CMP. Stud recesses are formed in the oxide using photolithography and RIE that either partially etches through the oxide or traverses the oxide and stops on the underlying metal to be contacted. The wire recesses can then be formed using a separate photolithography step and a timed oxide etching step. If the former stud RIE option is used, the wire etching completes the drilling of the stud holes.
Next, the stud/wire metallization is deposited, then planarized using CMP. The resulting interconnects are produced with fewer process steps than with conventional processing and with the dual damascene process, two layer of metal are formed as one, i.e., wiring line and contact stud vias, avoiding an interface between the layers.
Another metal deposition, besides sputtering techniques, has been adapted as a standard for copper metallization. This technique is electrochemical deposition (ECD) of copper. The electrochemical copper deposition (ECD) still needs, e.g., sputtering techniques, physical vapor deposition (PVD), to deposit thin underlying diffusion barrier film (Ta,TaN) and a conductive xe2x80x9cseedxe2x80x9d layer of copper.
The key points of Prior Art for copper dual damascene wire bonding, are that poor wire bonding occurs at the bond when bonding directly to pure copper. Brittle intermetallic compounds form directing between the lead-tin solder and the pure copper metal, among others that are possible, e.g., Cu3Sn5, CuSn3. Another reason for difficulty in wire bonding to the pure copper, is that the copper oxide does not form a passivating oxide and spalls or flakes off. Some metals, e.g., aluminum oxide Al2O3, Cr2O3, NiO, CoO, and insulating SiO2, form dense, passivating oxide, while copper oxide has a Pilling-Bedworth ratio much greater than one and forms oxides that are non-protecting, making the pure copper surface easy to oxidize and less noble than the other materials. Standard wire bond pull strengths are reduced to unacceptable levels resulting in spalling, peeling and fracture of the wire bond at the Cu/Pb-Sn interface, by the pure copper dual damascene Prior Art methods. As an example of goodness, needed for good results in wire bond tensile strength tests, is that the wire itself is broken, at tensile force levels approaching the tensile strength of the appropriate wire, and not at the wire bond itself.
Related Prior Art background patents will now be described in this section.
U.S. Pat. No. 5,989,993 entitled xe2x80x9cMethod for Galvanic Forming of Bonding Padsxe2x80x9d granted Nov. 23, 1999 to Zakel et al. describes a plating process for a bonding pad. A method for the preparation of electrodeposited or galvanically deposited bumps for the bonding of integrated circuits is shown. It is characterized by two subsequent metal depositions, deposited without an external current source (chemical metal deposition) on a metallization.
U.S. Pat. No. 5,785,236 entitled xe2x80x9cAdvanced Copper Interconnect System That Is Compatible With Existing IC Wire Bonding Technologyxe2x80x9d granted Jul. 28, 1998 to Cheung et al. describes a copper bonding pad process. A process is provided which enables electrical connection to be formed between gold and aluminum wires and copper interconnects. Conventional techniques for wire bonding are ineffective for bonding gold wires or aluminum wires to copper pads or copper interconnects. The patent describes a process whereby an aluminum pad is formed over the copper interconnects. Metal wire is then bonded to the aluminum pad using conventional wire bonding techniques.
U.S. Pat. No. 5,985,765 entitled xe2x80x9cMethod For Reducing Bonding Pad Loss Using a Capping Layer When Etching Bonding Pad Passivation Openingsxe2x80x9d granted Nov. 16, 1999 to Hsiao et al. teaches a bonding pad with an overlying capping layer. A method for reducing bonding pad loss is described using a capping layer when contact openings are etched to the bonding pads, while concurrently etching much deeper fuse openings to the substrate. Bonding pads are used on the top surface of integrated circuit semiconductor chips to provide external electrical connections for I/Os and power. Fusible links are used in the underlying insulating layers to remove redundant defective circuit elements, and thereby, repair defective chips. It is desirable (cost effective) to etch the contact openings in the passivation layer to the bonding pads near the top surface on the chip and to concurrently etch the much deeper fuse openings in the thick underlying insulating layers over the fuses. However, because of the difference in etch depth of the two types of openings, the bonding pads composed of Al/Cu are generally overetched causing bond-pad reliability problems. This invention describes a process in which a capping layer, having a low etch rate, is formed on the bonding pads to prevent overetching, while the fuse openings are etched to the desired depth in the thicker insulating layers.
U.S. Pat. No. 5,923,955 entitled xe2x80x9cFine Flip Chip Interconnectionxe2x80x9d granted Jul. 13, 1999 to Wong shows a multi-layed bonding pad. There is disclosed a process for creating a flip chip bonded combination for a first integrated circuit and a second integrated circuit. Creating a first connection means on each bonding pad of a first integrated circuit within a first wall structure and a second connection means on each bonding pad of a second integrated circuit within a second wall structure. Removing the second wall structure and partially placing each second connection means within the first wall structure over a respective connection means of the first integrated circuit.
It is the object of the present invention to provide processes wherein special Alxe2x80x94Cu bond layers or regions are placed on top of the underlying copper pad metal. These Alxe2x80x94Cu bond pads on pure copper (with barrier layer in-between) provide for improved wire bond adhesion to the bond pads and prevent peeling during wire bond adhesion tests.
The first embodiment of the present invention is now summarized, the first method of formation for an Alxe2x80x94Cu alloy top bond pad region for subsequent wire bonding. Provided is a dual copper damascene processing scheme and structure in intermetal dielectric (IMD) layers, with copper metallurgy within and wiring underneath, on a provided semiconductor substrate. Excess copper is polished back by chemical mechanical polishing (CMP), using a passivating cap layer, e.g., silicon nitride, as a CMP stop layer. Selective wet etching of the top layer of copper is performed by a DMSO/CCl4 solution. This wet etching step yields a recessed top metal copper layer. A hydrogen or ammonia plasma is performed to remove any copper oxide on the top copper layer. Next, a barrier layer is deposited by either a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD). A blanket layer of AlCu alloy metal is deposited by physical vapor deposition (PVD) sputtering the AlCu film. Patterning of the Alxe2x80x94Cu film and barrier layer is performed, wherein, the Alxe2x80x94Cu and barrier layer is reactive ion etched back (RIE) using Cl2/BCl3 chemistry, stopping on the silicon nitride cap. Alternately, the Alxe2x80x94Cu and barrier layer, TiN, is polished back using chemical mechanical polishing (CMP), stopping on the silicon nitride cap. The end result of the first embodiment of this invention is an Alxe2x80x94Cu bond pad on top of the entire dual damascene copper (barrier layer in between), interconnect trench and via. The top Alxe2x80x94Cu bond pad layer can now be soldered without the need for further passivation.
The second embodiment of the present invention is now summarized, the first method of formation for an Alxe2x80x94Cu alloy top bond pad region for subsequent wire bonding. Provided is a dual copper damascene processing scheme and structure in intermetal dielectric (IMD) layers, with copper metallurgy within and wiring underneath, on a provided semiconductor substrate. Excess copper is polished back by chemical mechanical polishing (CMP), using a passivating cap layer, e.g., silicon nitride, as a CMP stop layer. A lithography step patterns photoresist and the top copper is wet etched by DMSO/CCl4 to form a patterned recessed copper layer. The photoresist is stripped using an oxygen plasma ash step or using a solvent stripper. Next, an optional hydrogen or ammonia gas plasma treatment is used to remove any copper oxide on the surface. Barrier metal is deposited using chemical vapor deposition (CVD) or physical vapor deposition (PVD). Following the barrier metal deposition, a layer of Alxe2x80x94Cu alloy metal is deposited. Patterning of the Alxe2x80x94Cu film and barrier layer is performed, wherein the Alxe2x80x94Cu and barrier layer is reactive ion etched back (RIE) using Cl2/BCl3 chemistry, stopping on the silicon nitride cap. Alternately, the Alxe2x80x94Cu and barrier layer is polished back using chemical mechanical polishing (CMP), stopping on the silicon nitride cap. The end result of the second embodiment of this invention is an Alxe2x80x94Cu bond pad centrally located over the dual damascene copper (barrier layer in between), interconnect trench and contact via. The top Alxe2x80x94Cu bond pad layer can now be soldered without the need for further passivation.
The third embodiment of the present invention is now summarized, the first method of formation for an Alxe2x80x94Cu alloy top bond pad region for subsequent wire bonding. Provided is a dual copper damascene processing scheme and structure in intermetal dielectric (IMD) layers, with copper metallurgy within and wiring underneath, on a provided semiconductor substrate. Excess copper is polished back by chemical mechanical polishing (CMP), stopping on an intermetal dielectric (IMD) layer. A passivating layer of silicon nitride is blanket deposited over the substrate and covers the top surface of copper and intermetal dielectric (IMD). Next, a lithography step patterns photoresist, which patterns the silicon nitride passivating layer. The passivating nitride is reactive ion etched (RIE). In addition, the top copper is patterned, wherein the top copper is reactive ion etched (RIE), or wet etched, to form a patterned recessed copper layer. Next, the photoresist is stripped using an oxygen plasma ash step or using a solvent stripper. A hydrogen or ammonia gas plasma is used to remove any copper oxide on the copper surface. Barrier metal is deposited using chemical vapor deposition (CVD) or physical vapor deposition (PVD). Following the barrier metal deposition, a layer of Alxe2x80x94Cu alloy metal is deposited, forming the start of an Alxe2x80x94Cu bonding pad region. Patterning of the Alxe2x80x94Cu film and barrier layer is performed, wherein is the Alxe2x80x94Cu and barrier layer is reactive ion etched back (RIE) using Cl2/BCl3 chemistry, stopping on the silicon nitride passivating layer. Alternately, the Alxe2x80x94Cu and barrier layer is polished back using chemical mechanical polishing (CMP), stopping on the silicon nitride passivating layer. The end result of the third embodiment of this invention is an Alxe2x80x94Cu bond pad, planar and centrally located planar over the dual damascene copper (barrier layer in between), interconnect trench and contact via. The top Alxe2x80x94Cu bond pad layer can now be soldered without the need for further passivation.
The processes of the present invention fabricate Alxe2x80x94Cu wire bonding pads that have good adhesion properties (no metal interface separation/peel failures or interface fracture failures). Since there are a large statistical number of these structures, failure rates are very low and show a high reliability, as tested by gold wire bond pull tests. Temperature and humidity cycling tests also indicate the robustness of the processes of this invention, free from stress-crack corrosion, peeling, interface failure, adhesion failures.
In summary, for all three main embodiments of the present invention, the top Alxe2x80x94Cu bond pad layer can be soldered without the need for further passivation. At the aluminum copper alloy interface is protected from the pure copper below by the barrier layer.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the xe2x80x9cDESCRIPTION OF THE PREFERRED EMBODIMENTSxe2x80x9d section.